The present invention generally relates to the field of electrically programmable and electrically erasable read-only memory, and more particularly to a filtered serial-event-controlled command port for a flash memory device.
The power and flexibility of personal computers have increased dramatically since their introduction in the marketplace. As a result, the use of computers has risen significantly and has had a tremendous impact in society. In essence, personal computers typically comprise a microprocessor chip, random access memory, and non-volatile memory. Non-volatile memory is memory that retains its previously stored information even when power is no longer supplied to the chip. One type of non-volatile memory is read-only flash memory, which can be erased electrically rather than by exposure to ultra-violet light. Read-only flash memories are also electrically programmable.
A variety of conceived memory-command interfaces has simplified reading and writing information to non-volatile memories coupled to microprocessors. With such an interface, a microprocessor can issue a command such as xe2x80x9cerasexe2x80x9d or xe2x80x9cprogramxe2x80x9d through data lines connecting the microprocessor to the memory chip. The chip typically contains logic circuitry for decoding and executing these commands.
The prior art employs different methods for implementing this logic circuitry. FIG. 1 depicts an example of one implementation, disclosed in U.S. Pat. No. 5,222,046. To request the execution of a command, the control lines of the microprocessor externally generates an asynchronous clock signal by bringing lines chip enable and write enable {overscore (CE)} and {overscore (WE)} low. Typically, a clock signal lasts approximately 50 nanoseconds (ns), and the time between successive clock signals is even shorter, approaching 10 nanoseconds (ns).
Such a short duration, however, can potentially disrupt the logic circuitry of a memory device from properly executing a desired command. Typically, data latches into the command and state registers incident to the externally generated asynchronous clock signal. The state decoder block then decodes the output of the registers and directs execution of the proper command. However, the parasitic capacitance associated with the chip typically delays movement of data through the data bus to the registers. Before the data reaches the registers, the microprocessor may generate another clock signal asking for a second command to be performed on different data. Potentially, this may confuse the decoder block, causing it to direct execution of the second command on the wrong data, and to fail to execute the first command.
For example, the microprocessor may request execution of a first command on a first data. The state decoder block will receive this command, and begin waiting for the first data to move through the data bus to the state and command registers. Before the data reaches the registers, however, the microprocessor may request execution of a second command on a second data. The decoder block may receive this second command before the first data has reached the registers. When the first data does arrive, the block will direct execution of the second command on the first data, thus directing performance of the wrong command on the first data. Therefore, a drawback to the approach employed by the prior art is that extreme care must be taken in designing a non-volatile memory device chip so as to prevent this problem from occurring.
It should be noted, however, that typically once a command is received by the command architecture, it latches therein such that subsequent data received by the architecture will have the last received command performed upon it. For example, in the sequence COMMAND-DATA1-DATA2, both DATA1 and DATA2 will have COMMAND performed upon them. In other words, each sent data does not require a separately sent commandxe2x80x94the command COMMAND-DATA1-COMMAND-DATA2 is not necessary, for example, to perform COMMAND on both DATA1 and DATA2. Furthermore, where the command architecture has initially powered up and no command has yet been sent to it, typically the default command in such an instance is a read command.
This parallel approach to command architecture also poses a problem because of the simultaneous nature of the command and state processing inherent in a parallel approach. The state register must read and process data off the bus concurrent to the command register reading and processing a command off the bus. The registers must output to the state decoder block the results of their processing nearly simultaneously, or the state decoder will not direct execution of the command upon the data correctly. In using a non-volatile memory employing the prior art approach to command architecture, a designer must take proper precaution to avoid this situation from occurring.
In addition, the approach taken by the prior art is highly sensitive to noise on the {overscore (WE)} and {overscore (CE)} lines. The internal logic circuitry of a non-volatile memory device may potentially perceive even a brief burst of simultaneous noise on the {overscore (WE)} and {overscore (CE)} lines as an asynchronous clock signal generated externally by the microprocessor. This would erroneously cause the state and command registers to latch, and the state decoder block to decode. The decoder block would then direct execution of a command upon data in the device that the microprocessor had not actually requested. Therefore, a drawback to the approach employed by the prior art is that it is vulnerable to noise on the {overscore (CE)} and {overscore (WE)} lines inciting erroneous commands to be executed upon data in the memory device.
This problem is exasperated in many systems where the {overscore (CE)} line is typically tied low. Noise on the {overscore (WE)} line is then sufficient to incite erroneous execution of a command. A command architecture might divide execution of an erase command into two parts: an erase-setup command for directing the command to occur, and an erase-confirm command for verifying that the command has executed. Even if the erase-setup command executes properly, noise on the {overscore (WE)} line before the command register has received the erase-confirm command will frustrate proper execution of the operation. This is because after handling the erase-setup command, the state register expects to receive a erase-confirm command. When it does not, it signals an error, even if the next command on the bus is a erase-confirm command. A prior-art memory device operating in such a noisy environment may thus encounter curtailed performance.
The present invention is directed to a circuit to filter any signals asserted on lines {overscore (WE)} and {overscore (CE)} less than a predetermined duration, and to execute processing of a command and state within the command architecture in a serial manner. The circuit of the invention eliminates the potential for the state block decoder to direct execution of a wrong command because the duration is necessarily longer than the delay in data moving through the data bus to the register. The circuit of the invention also eliminates the potential for erroneous execution because a single register handles both data and command information off the bus, processing it in a serial manner. Further, the circuit of the invention eliminates vulnerability to noise that may cause the decoder to direct execution of an erroneous command, because typically such noise is shorter in duration than that which the invention allows to pass.
These and other advantages and features that characterize the present invention are described with particularity in the claims appended hereto and forming a further part hereto. For better understanding of the invention, its advantages and objectives, reference should be made to the drawings, which form a further part hereto, and to the accompanying descriptive matter, which illustrates and describes a preferred embodiment of the present invention.